One of the biggest steps in the history of computing was the integration of an entire CPU on a single chip. The so born microprocessor made the microcomputer possible, which would eventually bring affordable personal computing to the masses. This technological advancement came with just one small downside: the new microprocessors were even more of a black box (often literally) than the older multi-component CPU boards. One consequence of this is that today the study of CPU design is usually purely abstract, with few opportunities for any hands-on exercises.
In 1994, Bradford J. Rodriguez published the design of an experimental “old-school” CPU board, intended for teaching fundamentals of CPU design. His paper “A Minimal TTL Processor for Architecture Exploration” discusses the basic design of the “Pathetic Instruction Set Computer” (PISC), plus a series of increasingly complex design extensions.
The most basic PISC processor can be built of 22 standard TTL chips plus some external RAM and ROM, which makes its construction a realistic student project. Its design is fully static, meaning that it can be operated at a variety of clock speeds and even single stepped to investigate its internal operations.
The PISC uses only 16 internal control signals. This makes it feasible to define a 16-bit wide instruction set, which is simply made up of the bit pattern that needs to be fed into the internal control lines to operate the processor. Hence, no instruction decoding is required, which further simplifies the design.
The PISC has a 16-bit wide ALU, which is constructed of four 4-bit wide 74181s operating on different bit groups in parallel. This ALU provides all the usual add, subtract, and logic functions, 32 different operations in total. Selecting a specific ALU operation requires 5 control lines, which are programmed using 5 bits of each instruction word. The inputs and output of the ALU are connected to a register file of eight 16-bit registers. Which registers are selected as inputs and output, is determined by three control lines each, adding up to 9 bits to the instruction word. Finally, in addition to these internal operations, which only involve the ALU and the register file, the PISC also has some special logic to enable loads and stores from and to memory, which are selected using the remaining two instruction bits. The program counter is implemented as one of the eight registers, which hence becomes a special purpose register. Its direct manipulation by the ALU or by a load instruction can be used to implement unconditional jumps.
The basic PISC processor includes most features of a regular CPU, but it also presents some critical deficiencies: among others, it lacks conditional branch instructions, a way to load literal values from program store, and each instruction requires two separate fetch and execute cycles. The second part of Rodriguez’ paper discusses different ways to overcome some of these deficiencies without adding significant complexity to the PISC design. Some of these additions are rather straight forward, and are recommended as exercises for students, while others lead directly into advanced topics of CPU design, such as pipelining, or the RISC versus CISC discussion.
I just stumbled upon Rodriguez’ paper by chance, but read it with great fascination. Having some minimal background in electronic engineering, the PISC design served me as an eye-opener to better understand the interactions between ALU, registers, and all the rest that acts together as the CPU control unit. I think, that actually building a PISC and trying to optimize it might be a fun exercise. Unfortunately, it would be also rather time consuming… and time is something in rather short supply to me these days. But anyhow, it was a very enjoyable and informative read! Admitted, it’s a bit geeky… but if that’s the way you feel, have a look at it.